1. Field of the Invention
The present invention relates to an integrated circuit device and manufacturing method thereof. More particularly, the present invention relates to a metal oxide semiconductor (MOS) transistor structure and manufacturing method thereof.
2. Description of the Related Art
With the reduction of line width in metal oxide semiconductor (MOS) fabrication, leakage current in areas between the source and the drain away from the gate is increasingly significant. Although the leakage current can be reduced through a reduction in the thickness of the gate dielectric layer, it is no longer effective when the line width drops to 0.1 μm or below. To deal with this problem, Professor Chenming Hu of the University of California at Berkley has proposed two methods. The first method is to use an extremely thin first doping type semiconductor substrate to fabricate MOSFET so that the substrate no longer has an area away from the gate and hence a leakage current no longer exists. The second method is to use a double gate structure. A gate dielectric layer in the double gate structure surrounds the channel region so that the entire channel region is subjected to the influence of the gate electric field. Ultimately, the ‘on’ current of the device is increased and the leakage current is reduced.
A fin-type field effect transistor (FinFET) that combines the two aforementioned concepts is shown in FIGS. 1A to 1C. FIG. 1A is a top view of a conventional FinFET device. FIGS. 1B and 1C are schematic cross-sectional views along the cutting lines I–I′ and II–II′ in FIG. 1A. The fin-type field effect transistor is formed in the following steps. First, a silicon-on-insulator (SOI) substrate 100 is provided. The silicon layer (not shown, but is a precursor of the layer labeled 120) on the insulation layer 105 has a thickness of about 100 nm. A thermal oxidation process is carried out to trim the silicon layer into one having a thickness of about 50 nm. Thereafter, a masking layer 110 fabricated from a low-temperature oxide (LTO) material is formed over the silicon layer. After that, a 100 KeV electron beam photolithographic and anisotropic etching process is carried out to define the hard masking layer 110 and the silicon layer. Hence, a fin-like silicon layer 120 having a width between 20 nm to 50 nm is formed. The narrowness of the silicon layer 120 can be seen in FIGS. 1A through 1C. Next, a polysilicon silicon-germanium (poly Si—Ge) layer (not shown, but is a precursor of the layers labeled 140 and 150) and a hard masking layer 130 fabricated from a low-temperature oxide material are sequentially formed over the substrate 100. The poly Si—Ge layer and the hard masking layer 130 are patterned to form a raised source 140 and a drain 150 having a thickness much larger than the fin-like silicon layer 120.
Thereafter, a silicon nitride layer (not shown, but is a precursor to the layer labeled 160) is formed over the SOI substrate 100 and then an anisotropic etching operation is carried out to form spacers 160. In the anisotropic etching operation, an over-etching operation is carried out after the silicon nitride layer on the hard masking 130 is completely removed. Thus, the thin silicon nitride layer on the sidewalls of the fin-like silicon layer 120 is completely removed while spacers 160 are retained on the sidewalls of the raised source 140 and drain 150 as shown in FIGS. 1A and 1B. Thereafter, the sidewalls of the fin-like silicon layer 120 are oxidized to form gate oxide layers 170. Another polysilicon silicon-germanium (not shown, but is the precursor to the layer labeled 180) is formed over the SOI substrate 100 filling the gap 190 between the spacers 160. After that, the polysilicon silicon-germanium layer is patterned to form a gate 180.
In the aforementioned method of fabricating the FinFET, an electron beam photolithographic process is used to define the fin-like silicon layer 120. Hence, the fin-like silicon layer 120 can be reduced to a width between 20 nm to 50 nm to prevent a leakage current. In addition, as shown in FIGS. 1A and 1C, the two sidewalls of the fin-like silicon layer 120 are designed to sense the electric field produced by the gate 180. Hence, the device can have a larger ‘on’ current. However, the devices need to be formed on an expensive silicon-on-insulator substrate, thereby increasing the production cost. Besides, the FinFET fabrication process involves some quite complicated steps.